View K9GAG08U0E_7156683.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

- 1 - K9GAG08U0E rev. 0.9.1,mar. 2010 samsung electronics reserves the right to change products, information and specifications without notice. products and specifications discussed herein are for reference pur poses only. all info rmation discussed herein is provided on an "as is" bas is, without warranties of any kind. this document and all information discussed herein re main the sole and exclusive property of samsung electronics. no license of any patent, copyright, mask work, tradem ark or any other intellectual property right is granted by one party to the other party under this document, by implication, estoppel or other- wise. samsung products are not intended for use in life sup port, critical care, medical, safety equipment, or similar applications where pr oduct failure could result in loss of li fe or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. for updates or additional information about samsung products, contact your nearest samsung office. all brand names, trademarks and registered tradem arks belong to their respective owners. ? 2010 samsung electronics co., ltd. all rights reserved. k9lbg08u0e k9hcg08u1e final 16gb e-die nand flash multi-level-cell (2bit/cell) datasheet free datasheet http:///
- 2 - datasheet flash memory rev. 0.9.1 k9lbg08u0e final K9GAG08U0E k9hcg08u1e revision history revision no. history draft date remark editor 0.0 1. initial issue jun. 12, 2009 advance 0.1 1. pin configuration is changed. 2. trea is changed from 20ns to 25ns. 3. memory cell array is amended. 4. row address is modified. 5. dummy busy time for two-plane program(tdbsy) is deleted. oct. 21, 2009 advance 0.2 1. pin configuration is changed. oct. 21, 2009 advance 0.3 1. trc/twc is changed from 30ns to 20ns. 2. the parameter related trc/twc is changed nov. 6, 2009 advance 0.4 1. 52lga (11x14) qdp is added nov. 13, 2009 advance s.m.lee 0.5 1. ac character?s changed. jan. 20, 2010 advance s.m.lee 0.9 1. part id k9lbg08u0e and k9hcg08u1e are added. mar. 09, 2010 final s.m.lee 0.9.1 1. tr 300->400 changed. 2. k9hcg08u5e is deleted. 3.package dimensions of 48-tsop are amended. mar. 31, 2010 final s.m.lee free datasheet http:///
- 3 - table of contents datasheet flash memory rev. 0.9.1 k9lbg08u0e final K9GAG08U0E k9hcg08u1e 1.0 introduction ........... .............. .............. .............. .............. ............ ........... ........... .......... ......................................... 5 1.1 product list............................................................................................................... ............................................... 5 1.2 features ............................................................... ............................................................... .............................5 1.3 general description........................................................................................................ ......................................... 5 1.4 pin configuration (tsop1).................................................................................................. .................................... 6 1.5 package dimensions ................ .............. .............. .............. .............. ............ ........... .......... ...................................... 6 1.6 pin configuration (48tsop) ................................................................................................. ......................... 7 1.6.1package dimensions ........................................................................................................ .......................... 7 1.7 pin description ............................................................................................................ ............................................ 8 2.0 product introduction....................................................................................................... ............................... 10 2.1 absolute maximum ratings ...... ............................................................................................. .................................. 11 2.2 recommended operating conditions ..................... ...................................................................... .......................... 11 2.3 dc and operating characteristics(recommended operati ng conditions otherwise noted. ) ................ ........... ...... 11 2.4 valid block................................................................................................................ ............................................... 12 2.5 ac test condition .......................................................................................................... .......................................... 12 2.6 capacitance(ta=25c, vcc=3.3v, f=1.0mhz)................................................................................... ....................... 12 2.7 mode selection............................................................................................................. ........................................... 12 2.8 program / erase characteristics ............................................................... .........................................................13 2.9 ac timing characteristics for command / address / da ta input ............................................................... ............. 13 2.10 ac characteristics for operation................... ....................................................................... ................................. 14 3.0 nand flash technical notes ......... .............. .............. .............. .............. ............ ........... ......... ......................... 15 3.1 initial invalid block(s) ................................................................................................... ............................................ 15 3.2 initial invalid block(s) ................................................................................................... ............................................ 15 3.3 error in write or read operation........................................................................................... ..................................... 16 3.4 addressing for program operation ................... ........................................................................ ................................ 18 3.5 interleaving operation .................................................................................................... ......................................... 20 3.5.1interleaving page program ................................................................................................. ............................... 21 3.5.2interleaving page read.................................................................................................... .................................. 22 3.5.3 interleaving block erase ... .............................................................................................. .................................. 23 3.5.4interleaving read to page program......................................................................................... .......................... 24 3.5.5 interleaving copy-back progra m ........................................................................................... ........................... 25 3.6 system interface using ce don?t-care. ...................................................................................... ............................. 26 4.0 timing diagrams ............................................................................................................ ....................................... 27 4.1 command latch cycle ..... .............. .............. .............. .............. ........... ........... ............ ......... .................................... 27 4.2 address latch cycle........................................................................................................ ........................................ 27 4.3 input data latch cycle ..................................................................................................... ....................................... 28 4.4 * serial access cycle after read(cle=l, we=h, ale= l)....................................................................... ............... 28 4.5 serial access cycle after read(edo type, cle=l, we=h, ale=l) ............................................................... ...... 29 4.6 status read cycle.......................................................................................................... ......................................... 29 4.7 read operation ............................................................................................................. .......................................... 30 4.8 read operation(intercepted by ce) .......................................................................................... .............................. 30 4.9 random data output in a page ............................................................................................... ............................... 31 4.10 cache read operation(1/ 2) ............... .............. .............. .............. .............. .............. ............ ................................. 32 4.11 cache read operation(2/ 2) ............... .............. .............. .............. .............. .............. ............ ................................. 33 4.12 page program operation.................................................................................................... ................................... 34 4.13 page program operation with random data input ............................................................................. .................. 35 4.14 copy-back program operation with random data input ........................................................................ .............. 36 4.15 cache program operation(available only within a bl ock).................................................................... .................. 37 4.16 block erase operation..................................................................................................... ...................................... 38 4.17 read id operation......................................................................................................... ........................................ 39 4.17.1id definition table ............................................................... ............................................................... .......40 5.0 device operation ........................................................................................................... ..................................... 42 5.1 page read.................................................................................................................. ............................................. 42 5.2 cache read ................................................................................................................. ........................................ 43 5.3 page program ............................................................................................................... .......................................... 45 5.4 copy-back program.......................................................................................................... ....................................... 46 5.5 cache program .............................................................................................................. ......................................... 47 5.6 block erase ................................................................................................................ ............................................. 50 5.7 read status................................................................................................................ ............................................. 51 free datasheet http:///
- 4 - datasheet flash memory rev. 0.9.1 k9lbg08u0e final K9GAG08U0E k9hcg08u1e 5.8 read id .................................................................................................................... ............................................... 52 5.9 reset...................................................................................................................... ............................................... 52 5.10 ready/busy ................................................................................................................ ........................................... 53 6.0 data protection & power up sequence................ ........................................................................ ............. 54 6.1 wp ac timing guide ......................................................................................................... ...................................... 55 free datasheet http:///
- 5 - datasheet flash memory rev. 0.9.1 k9lbg08u0e final K9GAG08U0E k9hcg08u1e 1.0 introduction 1.1 product list 1.2 features ? ? ? ? ? ? ? ? ? ? ? ? part number density interface vcc range organization pkg type K9GAG08U0E-s 16gb conventional 2.7v ~ 3.6v x8 48tsop1 k9lbg08u0e-s 32gb k9hcg08u1e-s 64gb free datasheet http:///
- 6 - datasheet flash memory rev. 0.9.1 k9lbg08u0e final K9GAG08U0E k9hcg08u1e 1.4 pin configuration (48tsop) K9GAG08U0E-scb0/sib0 48-pin tsop1 standard type 12mm x 20mm 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 n.c n.c n.c n.c n.c n.c r/b re ce n.c n.c vcc vss n.c n.c cle ale we wp n.c n.c n.c n.c n.c n.c n.c n.c n.c i/o7 i/o6 i/o5 i/o4 n.c n.c vcc vss n.c n.c n.c i/o3 i/o2 i/o1 i/o0 n.c n.c n.c n.c n.c k9lbg08u0e-scb0/sib0 1.4.1 package dimensions 48-pin lead free plastic thin small out-line package type(i) 48 - tsop1 - 1220af unit :mm #1 #24 0.50typ [0.50 ) . . (r0.15) ( r0 .15) (10 ) . ) ) . free datasheet http:///
- 7 - datasheet flash memory rev. 0.9.1 k9lbg08u0e final K9GAG08U0E k9hcg08u1e 1.5 pin configuration (48tsop) 48-pin tsop1 standard type 12mm x 20mm 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 n.c n.c n.c n.c n.c r/b2 r/b1 re ce1 ce2 n.c vcc vss n.c n.c cle ale we wp n.c n.c n.c n.c n.c n.c n.c n.c n.c i/o7 i/o6 i/o5 i/o4 n.c n.c n.c vcc vss n.c n.c n.c i/o3 i/o2 i/o1 i/o0 n.c n.c n.c n.c k9hcg08u1e -scb0/sib0 1.5.1 package dimensions 48-pin lead/lead free plastic thin small out-line package type(i) 48 - tsop1 - 1220bf unit :mm #1 #24 0.50typ [0.50 ) . . ( r 0.15) (r0.15) (10 ) 5. ) ) . free datasheet http:///
- 8 - datasheet flash memory rev. 0.9.1 k9lbg08u0e final K9GAG08U0E k9hcg08u1e 1.6 pin description note : connect all vcc and vss pins of each de vice to common power supply outputs. do not leave vcc or vss disconnected. pin name pin function i/o 0 ~ i/o 7 data inputs/outputs the i/o pins are used to input command, address and data, and to output data during read operations. the i/o pins float to high-z when the chip is deselected or when the outputs are disabled. cle command latch enable the cle input controls the activating path for commands sent to the command register. when active high, commands are latched into the command register through the i/o ports on the rising edge of the we signal. ale address latch enable the ale input controls the activating path for address to the internal address registers. addresses are latched on the rising edge of we with ale high. ce chip enable the ce input is the device selection control. when the device is in the busy state, ce high is ignored, and the device does not return to standby mode in program or erase operation. re read enable the re input is the serial data-out control, and when active drives the data onto the i/o bus. data is valid trea after the fall- ing edge of re which also increments the inter nal column address counter by one. we write enable the we input controls writes to the i/o port. commands, address and data are latched on the rising edge of the we pulse. wp write protect the wp pin provides inadvertent program/eras e protection during power transitions. the internal high voltage generator is reset when the wp pin is active low. r/b ready/busy output the r/b output indicates the status of the device operation. when low, it indicates that a program, erase or random read operation is in process and returns to high state upon completi on. it is an open drain output and does not float to high-z con- dition when the chip is deselect ed or when outputs are disabled. vcc power v cc is the power supply for device. vss ground n.c no connection lead is not internally connected. free datasheet http:///
v cc x-buffers command i/o buffers & latches latches & decoders y-buffers latches & decoders register control logic & high voltage generator global buffers output driver v ss a 14 - a 33 a 0 - a 13 command ce re we cle wp i/0 0 i/0 7 v cc v ss ale (16,608m + 883.9m)bits nand flash array (8,192 + 436)byte x 265,728 y-gating data register & s/a figure 1. K9GAG08U0E functional block diagram figure 2. K9GAG08U0E array organization 8k bytes 436 bytes (=2,076 blocks) 8k bytes 8 bit 436 bytes 1 block = 128 pages (1m + 54.5k)bytes i/o 0 ~ i/o 7 1 page = (8k + 436)bytes 1 block = (8k + 436)b x 128 pages = (1m + 54.5k) bytes = 17,491 mbits page register 265,728 pages - 9 - datasheet flash memory rev. 0.9.1 k9lbg08u0e final K9GAG08U0E k9hcg08u1e note : column address : starting address of the register. * l must be set to ?low?. * the device ignores any additional input of address cycles than required. * row address consists of page address (a14 ~ a20) & block address(a21 ~ the last address) i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 1st cycle a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 2nd cycle a 8 a 9 a 10 a 11 a 12 a 13 *l *l 3rd cycle a 14 a 15 a 16 a 17 a 18 a 19 a 20 a 21 4th cycle a 22 a 23 a 24 a 25 a 26 a 27 a 28 a 29 5th cycle a 30 a 31 a 32 a 33 **l*l*l*l row address; column address block address : a 21 ~ a 32 page address : a 14 ~ a 20 *a 33 : chip address for k9lbg08u0e, k9hcg08u1e free datasheet http:///
- 10 - datasheet flash memory rev. 0.9.1 k9lbg08u0e final K9GAG08U0E k9hcg08u1e 2.0 product introduction nand flash memory has addresses multiplexed into 8 i/os. this scheme dramatic ally reduces pin counts and allows system upgrades to future densities by maintaining consistency in system board design. command, address and data are all wri tten through i/o's by bringing we to low while ce is low. those are latched on the rising edge of we . command latch enable(cle) and address latch enable(ale) are used to multiplex command and address respectively, via the i/o pins. so me commands require one bus cycle. for example, reset command, status read command, etc. require just one cycle bus. some other commands, like page read and block erase and p age program, require two cycles: one cycle for setup and the othe r cycle for execution. . page read and page program need the same five address cycles following the required co mmand input. in block erase operation, ho wever, only the three row address cycles are used. device operations are selected by writing specific commands in to the command register. the t able below defines the specific commands. [table 1] command sets note : 1) random data input/output can be executed in a page. caution : any undefined command inputs are prohibited except for above command set of table 1. function 1st set 2nd set acceptable command during busy read 00h 30h read for copy back 00h 35h cache read 31h - read start for last page cache read 3fh - page program 80h 10h cache program 80h 15h copy-back program 85h 10h block erase 60h d0h random data input (1) 85h - random data output (1) 05h e0h read id 90h - read status 70h - o chip status1 f1h - o chip status2 f2h o reset ffh - o free datasheet http:///
- 11 - datasheet flash memory rev. 0.9.1 k9lbg08u0e final K9GAG08U0E k9hcg08u1e 2.1 absolute maximum ratings note : 1) minimum dc voltage is -0.6v on input/output pins. during tran sitions, this level may undershoo t to -2.0v for periods <30ns. maximum dc voltage on input/output pins is vcc+0.3v which, during transitions, may overshoot to vcc+2.0v for periods <20ns. 2) permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet . exposure to absolute maximum rating conditions for extended peri ods may affect reliability. 2.2 recommended operating conditions (voltage reference to gnd, k9xxg08xxe-xcb0 : t a =0 to 70 q c (1) , k9xxg08xxe-xib0 : t a =-40 to 85 q c (1) ) note: 1) data retention is not guaranteed on operating condition temperature over/under. 2.3 dc and operating characteristics(recommende d operating conditions otherwise noted.) note : 1) v il can undershoot to -0.4v and v ih can overshoot to v cc +0.4v for durations of 20 ns or less. 2) typical value is measured at vcc=3.3v, t a =25 q c. not 100% tested. 3) the typical value of the k9lbg08u0e?s isb is 20 p a and the maximum value is100 p a the typical value of the k9hcg08u1e?s isb is 40 p a and the maximum value is200 p a 4) the typical value of k9lbg08u0e, k9hcg08u1e?s icc1, i cc2 and icc3 are 35ma and the maximum values are 55ma. 5) the maximum value of k9lbg08u0e?s is 20 p a. the maximum value of k9hcg08u1e?s is 40 p a. parameter symbol rating unit voltage on any pin relative to v ss v cc -0.6 to + 4.6 v v in -0.6 to + 4.6 v i/o -0.6 to vcc+0.3 (<4.6v) storage temperature k9xxg08uxe-xcb0 t stg -65 to +100 q c k9xxg08uxe-xib0 short circuit current ios 5 ma parameter symbol min typ. max unit supply voltage v cc 2.7 3.3 3.6 v supply voltage v ss 000v parameter symbol test conditions min typ max unit operating current page read with serial access i cc 1 (4) trc=30ns ce =v il, i out =0ma -3050ma program i cc 2 (4) - erase i cc 3 (4) - stand-by current(cmos) i sb (3) ce =v cc -0.2, wp =0v/v cc -1050 p a input leakage current i li (5) v in =0 to vcc(max) - - 10 output leakage current i lo (5) v out =0 to vcc(max) - - 10 input high voltage v ih (1) - 0.8 xvcc - vcc +0.3 v input low voltage, all inputs v il (1) - -0.3 - 0.2 xvcc output high voltage level v oh K9GAG08U0E :i oh =-400 p a2.4-- output low voltage level v ol K9GAG08U0E :i ol =2.1ma - - 0.4 output low current(r/b )i ol (r/b ) K9GAG08U0E :v ol =0.4v 8 10 - ma free datasheet http:///
- 12 - datasheet flash memory rev. 0.9.1 k9lbg08u0e final K9GAG08U0E k9hcg08u1e 2.4 valid block note : 1) the device may include initial invalid blocks when first ship ped. additional invalid blocks may develop while being used. th e number of valid blocks is presented with both cases of invalid blocks considered. invalid blocks are defined as blocks that contain one or more bad bits which cause status f ailure during program and erase operation. do not erase or program factory-marked bad blocks. refer to the at tached technical notes for appropriate management of invalid bl ocks. 2) the 1st block, which is placed on 00h block address, is guaranteed to be a valid block at the time of shipment 2.5 ac test condition (k9xxg08xxe-xcb0 :t a =0 to 70 q c, k9xxg08xxe-xib0:t a =-40 to 85 q c, k9xxg08uxe: vcc=2.7v ~ 3.3v,unless otherwise noted) 2.6 capacitance ( t a =25 c, v cc =3.3v, f=1.0mhz) note : 1) capacitance is periodically sampled and not 100% tested. 2) c i/o(w) and c in(w) are tested at wafer level. 2.7 mode selection note : 1) x can be v il or v ih. 2) wp should be biased to cmos high or cmos low for standby. parameter symbol min typ. max unit K9GAG08U0E n vb 2,018 - 2,076 blocks k9lbg08u0e 4,036 4,152 k9hcg08u1e 8,072 8,304 parameter k9xxg08uxe input pulse levels 0v to vcc input rise and fall times 5ns input and output timing levels vcc/2 output load 1 ttl gate and cl=50pf item symbol test condition K9GAG08U0E k9lbg08u0e k9hcg08u1e unit min max min max min max input/output capacitance c i/o v il =0v - 8 - 13 - 23 pf c i/o(w)* - 5 - 10 - 20 pf input capacitance c in v in =0v - 8 - 13 - 23 pf c in(w)* - 5 - 10 - 20 pf cle ale ce we re wp mode hll hx read mode command input l h l h x address input(5clock) hll hh write mode command input l h l h h address input(5clock) l l l h h data input l l l h x data output x x x x h x during read(busy) x x x x x h during program(busy) x x x x x h during erase(busy) x x (1) x x x l write protect xxhxx 0v/v cc (2) stand-by free datasheet http:///
- 13 - datasheet flash memory rev. 0.9.1 k9lbg08u0e final K9GAG08U0E k9hcg08u1e 2.8 program / erase characteristics note : 1) typical program time is measured at vcc=3.3v, ta=25 q c. not 100% tested. 2) typical program time is defined as the time within which mo re than 50% of the whole pages are programed at 3.3v vcc and 25 q c temperature. 3) within a same block, program time(tprog) of page group a is faster than that of page group b. typical tprog is the average program time of the page group a and b(table 5). page group a: page 0, 1, 3, 5, 7, ... , 77,79,7b,7d page group b: page 2, 4, 6, 8, 0a, ... , 7a,7c,7e,7f 4) t cbsy depends on the timing between internal programming time and data in time. 2.9 ac timing characteristics for command / address / data input notes : 1. the transition of the corresponding control pins must occur only once while we is held low 2. tadl is the time from the we rising edge of final address cycle to the we rising edge of first data cycle parameter symbol min typ max unit program time t prog - 1.2 5ms dummy busy time for cache program t cbsy (4) --5ms number of partial program cycles in the same page nop - - 1 cycle block erase time t bers -1.510ms parameter symbol min max unit cle setup time t cls (1) 15 - ns cle hold time t clh 5-ns ce setup time t cs (1) 25 - ns ce hold time t ch 5-ns we pulse width t wp 15 - ns ale setup time t als (1) 15 - ns ale hold time t alh 5-ns data setup time t ds (1) 15 - ns data hold time t dh 5-ns write cycle time t wc 30 - ns we high hold time t wh 10 - ns address to data loading time t adl (2) 300 - ns free datasheet http:///
- 14 - datasheet flash memory rev. 0.9.1 k9lbg08u0e final K9GAG08U0E k9hcg08u1e 2.10 ac characteristics for operation note : 1) if reset command(ffh) is written at ready state, the device goes into busy for maxium 10us. parameter symbol min max unit data transfer from cell to register t r - 400 p s ale to re delay t ar 10 - ns cle to re delay t clr 10 - ns ready to re low t rr 20 - ns re pulse width t rp 15 - ns we high to busy t wb - 100 ns wp high to we low t ww 100 ns read cycle time t rc 30 - ns re access time t rea -25ns ce access time t cea -35ns re high to output hi-z t rhz - 100 ns ce high to output hi-z t chz -30ns ce high to ale or cle don?t care t csd 0-ns re high to output hold t rhoh 15 - ns re low to output hold t rloh 5-ns re high hold time t reh 10 - ns output hi-z to re low t ir 0-ns re high to we low t rhw 100 - ns we high to re low t whr 60 - ns device resetting time(read/program/erase) t rst - 10/30/500 (1) p s cache busy in read cache (following 31h and 3fh) t dcbsyr - 400 p s free datasheet http:///
- 15 - datasheet flash memory rev. 0.9.1 k9lbg08u0e final K9GAG08U0E k9hcg08u1e 3.0 nand flash technical notes 3.1 initial invalid block(s) initial invalid blocks are defined as blocks that contain one or more initial invalid bits whose reliability is not guaranteed by samsung. the information regarding the initial invalid block(s) is called the initial inva lid block information. devices with initial invalid block(s) h ave the same quality level as devices with all valid blocks and have the same ac and dc characteristics. an initial invalid block(s) does not affect the performance of valid block(s) because it is isolated from the bit line and the common source line by a sele ct transistor. the system design must be able to mask out the initial invalid block(s) via address mapping. the 1st block, which is pl aced on 00h block address, is guaranteed to be a valid block at the time of shipment . 3.2 initial invalid block(s) all device locations are erased(ffh) except locations where the in itial invalid block(s) informat ion is written prior to shipping. the initial invalid block(s) status is defined by the 1st byte in the spare area. samsung make s sure that the first or the last page of every initial invali d block has non-ffh data at the column address of 0 or 8,192.the initial invalid block information is also erasable in most cases, and it is impossible to reco ver the information once it has been erased. therefore, the system must be able to recognize t he initial invalid block(s) based on the initial invalid block in formation and create the initial invalid block table via the following sugges ted flow chart. any intentional erasure of the initial invalid block information is prohibited figure 3. flow chart to crea te initial invalid block table no yes read ffh check column 0 or 8192 of the last page block no = 1 end pass pass fail start block no. = block no. + 1 read ffh check column 0 or 8192 of the first page entry bad block 1) fail last block note : 1) no erase operation is allowed to detected bad block free datasheet http:///
- 16 - datasheet flash memory rev. 0.9.1 k9lbg08u0e final K9GAG08U0E k9hcg08u1e 3.3 error in write or read operation within its life time, additional invalid blocks may develop with nand flash memory. refer to the qualification report for the a ctual data. block replacement should be done upon erase or program error. ecc : error correcting code --> rs code or bch code etc. example) 24bit correction / 1k+54.5 byte program flow chart start i/o 6 = 1 ? i/o 0 = 0 ? no * write 80h write address write data write 10h read status register program completed or r/b = 1 ? program error yes no yes : if program operation results in an error, map out the block including the page in error and copy the * target data to another block. failure mode detection and countermeasure sequence write erase failure status read after erase --> block replacement program failure status read after program --> block replacement read up to 24 bit failure verify ecc -> ecc correction free datasheet http:///
- 17 - datasheet flash memory rev. 0.9.1 k9lbg08u0e final K9GAG08U0E k9hcg08u1e nand flash technical notes (continued) erase flow chart start i/o 6 = 1 ? i/o 0 = 0 ? no * write 60h write block address write d0h read status register or r/b = 1 ? erase error yes no : if erase operation results in an error, map out the failing block and replace it with another block. * erase completed yes read flow chart start verify ecc no write 00h write address read data ecc generation reclaim the error page read completed yes write 30h block replacement buffer memory of the controller. 1st block a block b (n-1)th nth (page) { { an error occurs. 1 2 * step1 when an error happens in the nth page of the bloc k ?a ? during erase or program operation. * step2 copy the data in the 1st ~ (n-1)th page to the same location of another free block. (block ?b?) * step3 then, copy the nth page data of the block ?a? in the buffer memory to the nth page of the block ?b?. * step4 do not erase or program block ?a? by creating an ?i nvalid block? t able or other appropriate scheme. free datasheet http:///
- 18 - datasheet flash memory rev. 0.9.1 k9lbg08u0e final K9GAG08U0E k9hcg08u1e 3.4 addressing for program operation within a block, the pages must be programm ed consecutively from the lsb (least signific ant bit) page of the block to msb (most significant bit) pages of the block. random page address programming is prohibited. in th is case, the definition of lsb page is the lsb among the pages t o be programmed. therefore, lsb doesn?t need to be page 0. from the lsb page to msb page data in: data (1) data (128) (1) (2) (3) (32) (128) data register page 0 page 1 page 2 page 31 page 127 ex.) random page program (prohibition) data in: data (1) data (128) (2) (32) (3) (1) (128) data register page 0 page 1 page 2 page 31 page 127 : : : : free datasheet http:///
- 19 - datasheet flash memory rev. 0.9.1 k9lbg08u0e final K9GAG08U0E k9hcg08u1e paired page address information note : when program operation is abnormally aborted (ex. power-down, reset), not only page data under program but also paired page dat a may be damaged. paired page address(1/2) paired page address(2/2) group a group b group a group b 00h 02h 3fh 42h 01h 04h 41h 44h 03h 06h 43h 46h 05h 08h 45h 48h 07h 0ah 47h 4ah 09h 0ch 49h 4ch 0bh 0eh 4bh 4eh 0dh 10h 4dh 50h 0fh 12h 4fh 52h 11h 14h 51h 54h 13h 16h 53h 56h 15h 18h 55h 58h 17h 1ah 57h 5ah 19h 1ch 59h 5ch 1bh 1eh 5bh 5eh 1dh 20h 5dh 60h 1fh 22h 5fh 62h 21h 24h 61h 64h 23h 26h 63h 66h 25h 28h 65h 68h 27h 2ah 67h 6ah 29h 2ch 69h 6ch 2bh 2eh 6bh 6eh 2dh 30h 6dh 70h 2fh 32h 6fh 72h 31h 34h 71h 74h 33h 36h 73h 76h 35h 38h 75h 78h 37h 3ah 77h 7ah 39h 3ch 79h 7ch 3bh 3eh 7bh 7eh 3dh 40h 7dh 7fh free datasheet http:///
- 20 - datasheet flash memory rev. 0.9.1 k9lbg08u0e final K9GAG08U0E k9hcg08u1e 3.5 interleaving operation k9lbg08u0e and k9hcg08u1e devices are composed of two chips sharing per ce pi n. they provide interleaving operation between tw o chips this interleaving operation improves the system throug hput almost twice compared to non-interleaving operation. at first, the host issues a operation command to one of the lsb ch ips, say (chip #1). due to ddp device goes into busy state. d uring this time, msb chip (chip #2) is in ready state. so it can ex ecute the operation command issued by the host. after the execution of operation by lsb chip (chip #1), it can execute another operation regardless of msb chip (chip #2). bef ore that the host needs to check the status of lsb chip (chip #1) by issuing f1h command. on ly when the status of lsb chip (chip #1) becomes ready status, host can issue another operation command. if lsb chip (chip #1) is in busy state, the host has to wait for lsb chip (chip #1) to get into read y state. similarly, msb chip (chip #2) can execute another operation afte r the completion of the previous operation. the host can monit or the status of msb chip (chip #2) by issuing f2h command. when msb chip (chip #2) show s ready state, host can issue another operation command to msb ch ip (chip #2). this interleaving algorithm improves the system throughput almost twice. the host c an issue page operation command to each chip individually. this reduces the time lag for the completion of operation. notes : during interleave operations , 70h command is prohibited. [table 2] f1h read status register definition note : 1. i/os defined ?not use? are recommended to be masked out when read status is being executed. [table 3] f2h read status register definition note : 1. i/os defined ?not use? are recommended to be masked out when read status is being executed. i/o no. page program block erase read definition i/o 0 chip1 pass/fail chip1 pass/fail not use pass : "0" fail : "1" i/o 1 plane pass/fail plane pass/fail not use pass : "0" fail : "1" i/o 2 not use not use not use don?t -cared i/o 3 not use not use not use don?t -cared i/o 4 not use not use not use don?t -cared i/o 5 not use not use not use don?t -cared i/o 6 ready/busy ready/busy ready/busy busy : "0" ready : "1" i/o 7 write protect write protect w rite protect protected : "0" not protected : "1" i/o no. page program block erase read definition i/o 0 chip2 pass/fail chip2 pass/fail not use pass : "0" fail : "1" i/o 1 plane pass/fail plane pass/fail not use pass : "0" fail : "1" i/o 2 not use not use not use don?t -cared i/o 3 not use not use not use don?t -cared i/o 4 not use not use not use don?t -cared i/o 5 not use not use not use don?t -cared i/o 6 ready/busy ready/busy ready/busy busy : "0" ready : "1" i/o 7 write protect write protect w rite protect protected : "0" not protected : "1" free datasheet http:///
- 21 - datasheet flash memory rev. 0.9.1 k9lbg08u0e final K9GAG08U0E k9hcg08u1e 3.5.1 interleaving page program r/b (#1) busy of chip #1 i/o x 80h 10h chip address : low add & data 80h 10h chip address : high add & data busy of chip #2 internal only internal only r/b ab r/b (#2) 1 busy of chip #1 f1h busy of chip #2 b c d another page program on chip #1 i/o6 ready busy "1" "0" 1 r/b (#1) i/o x internal only internal only r/b r/b (#2) f2h i/o6 ready busy "1" "0" state a : chip #1 is executing page program operation and chip #2 is in r eady state. so the host can issue page program command to chip # 2. state b : both chip #1 and chip #2 are executing page program operation. state c : page program on chip #1 is terminated, but page program on chip #2 is still operating. and the system should issue f1h /f2h command to detect the status of chip #1. if chip #1 is ready, status i/o6 is "1" and the syst em can issue another page program command to chip #1. state d : chip #1 an d chip #2 are ready. according to the above process, the system can opera te p age program on chip #1 and chip #2 alternately. free datasheet http:///
- 22 - datasheet flash memory rev. 0.9.1 k9lbg08u0e final K9GAG08U0E k9hcg08u1e 3.5.2 interleaving page read add 00h 30h 00h 30h f1h chip address: low chip address: high add i/o6 ready busy "1" "0" abc 1 r/b (#1) i/o x internal only r/b (#2) internal only r/b add 00h 05h chip address: low add e0h column address d r/b (#1) i/o x internal only r/b (#2) internal only r/b data out add 00h 1 add 05h col.add e0h data out e r/b (#1) i/o x internal only r/b (#2) internal only r/b 2 2 f2h i/o6 ready busy "1" "0" state a : chip #1 is executing page read operation, and chip #2 is in r eady state. so the host can issue page read command to chip #2. state b : both chip #1 and chip #2 are executing page read operation. state c : page read on chip #1 is completed and chip #2 is still executing page read operation. state d : before the host read the data, the host should check the ready/busy status for both chips by f1h and f2h commands. state e : ch ip #1 and chip #2 are ready. note : * f1h command is required to check the status of chip #1. f2h command is required to check the status of chip #2. free datasheet http:///
- 23 - datasheet flash memory rev. 0.9.1 k9lbg08u0e final K9GAG08U0E k9hcg08u1e 3.5.3 interleaving block erase r/b (#1) busy of chip #1 i/o x 60h d0h chip address : low add 60h d0h chip address : high add internal only r/b (#2) internal only ab r/b 1 f1h busy of chip #2 bc d another block erase on chip #1 i/o6 ready busy "1" "0" r/b (#1) i/o x internal only r/b (#2) internal only r/b 1 f2h i/o6 ready busy "1" "0" state a : chip #1 is executing block erase operation, and chip #2 is in re ady state. so the host can issue block erase command to chip #2 . state b : both chip #1 and chip #2 are executing block erase operation. state c : block erase on chip #1 is terminated, but block erase on chip #2 is still operating. and the system should issue f1h /f2h command to detect the status of chip #1. if chip #1 is ready, status i/o6 is "1" and the syst em can issue another block erase command to chip #1. state d : chip #1 and chip #2 are ready. according to the above process, th e system can operate block erase on chip #1 and chip #2 alternately. free datasheet http:///
- 24 - datasheet flash memory rev. 0.9.1 k9lbg08u0e final K9GAG08U0E k9hcg08u1e 3.5.4 interleaving re ad to page program r/b (#1) i/o x internal only r/b (#2) internal only r/b ab 10h 80h chip address : low add data in t prog of chip #1 t r of chip #2 30h 00h add chip address : high f2h 1 r/b (#1) i/o x internal only r/b (#2) internal only r/b c 05h 00h chip address : high add data out t prog of chip #1 add e0h column address f1h i/o6 ready busy "1" "0" d i/o6 ready busy "1" "0" 1 state a : chip #1 is executing page program operation, and chip #2 is in ready state. so the host can issue read command to chip #2. state b : both chip #1 is executing page program operation and chip #2 is executing read operation. state c : read operation on chip #2 is completed and chip #2 is ready for the next operation. chip #1 is still executing page program op eration. state d : both chip #1 and chip #2 are ready. note : *f1h command is required to check the status of chip #1 to issue the next command to chip #1. f2h command is required to check the status of chip #2 to issue the next command to chip #2. as the above process, the system can operate interleave read to page porgram on chip #1 and chip #2 alternatively. free datasheet http:///
- 25 - datasheet flash memory rev. 0.9.1 k9lbg08u0e final K9GAG08U0E k9hcg08u1e 3.5.5 interleaving copy-back program r/b (#1) i/o x internal only r/b (#2) internal only r/b 35h 00h chip address : low add i/o6 ready busy "1" "0" f1h 05h 00h add e0h add chip address : low column address t r of chip #1 1 i/o x r/b 1 bc t prog of chip #1 a 10h 85h chip address : low add & data 35h 00h chip address : high add t r of chip #2 i/o6 ready busy "1" "0" r/b (#1) internal only r/b (#2) internal only 2 00h r/b (#1) i/o x internal only r/b (#2) internal only r/b 2 10h 85h chip address : high add & data data out d 05h add e0h add column address chip address : high 3 e t prog of chip #2 i/o6 ready busy "1" "0" f r/b (#1) i/o x internal only r/b (#2) internal only r/b 3 f2h f1h f1h i/o6 ready busy "1" "0" f2h state a : chip #1 is executing copy-back program operation, and chip #2 is in ready state. so the host can issue read for copy-back comma nd to chip #2. state b : chip #1 is executing copy-back program operation an d chip #2 is executing read for copy-back operation. state c : re ad for copy-back operation on chip #2 is completed and chip #2 is ready for the next operation. chip #1 is still executing c opy-back program operation. state d : b oth chip #1 and chip #2 are executing copy-back program operation. state e : chip #2 is s till executing a copy-back program operation, and chip #1 is in ready for the next operation. state f : both chip #1 and chip #2 are ready. note : *f1h command is required to check the status of chip #1 to issue the next command to chip #1. f2h command is required to check the status of chip #2 to issue the next command to chip #2. as the above process, the system can operate interleave cop y-back program on chip #1 and chip #2 alternatively. free datasheet http:///
- 26 - datasheet flash memory rev. 0.9.1 k9lbg08u0e final K9GAG08U0E k9hcg08u1e 3.6 system interface using ce don?t-care. for an easier system interface, ce may be inactive during the data-loading or serial access as shown below. the internal 8,628byte data registers are utilized as separate buffers for this operation and the system des ign gets more flexible. in addition, for voice or audio appli cations which use slow cycle time on the order of figure 4. program operation with ce don?t-care. figure 5. read operation with ce don?t-care. address(5cycle) 00h ce cle ale we data output(serial access) ce don?t-care r/b t r re 30h i/ox ce we t wp t ch t cs address(5cycles) 80h data input ce cle ale we data input ce don?t-care 10h t cea out t rea ce re i/o 0 ~ 7 i/ox free datasheet http:///
- 27 - datasheet flash memory rev. 0.9.1 k9lbg08u0e final K9GAG08U0E k9hcg08u1e 4.0 timing diagrams 4.1 command latch cycle ce we cle ale command t cls t cs t clh t ch t wp t als t alh t ds t dh i/ox 4.2 address latch cycle ce we cle ale col. add1 t cs t wc t wp t als t ds t dh t alh t als t wh t wc t wp t ds t dh t alh t als t wh t wc t wp t ds t dh t alh t als t wh t ds t dh t wp i/ox col. add2 row add1 row add2 t wc t wh t alh t als t ds t dh row add3 t alh t cls free datasheet http:///
- 28 - datasheet flash memory rev. 0.9.1 k9lbg08u0e final K9GAG08U0E k9hcg08u1e 4.3 input data latch cycle ce cle we din 0 din 1 din final ale t als t clh t wc t ch t ds t dh t ds t dh t ds t dh t wp t wh t wp t wp i/ox re ce r/b dout dout dout t rc t rea t rr t rhoh t rea t reh t rea t rhz i/ox t chz t rhz notes : 1)transition is measured at free datasheet http:///
- 29 - datasheet flash memory rev. 0.9.1 k9lbg08u0e final K9GAG08U0E k9hcg08u1e 4.5 serial access cycle after read (edo type, cle=l, we =h, ale=l) re ce r/b i/ox dout dout t rea notes : 1) transition is measured at ce we cle re 70h/f1h/f2h status output t clr t clh t wp t ch t ds t dh t rea t ir t rhoh t whr t cea t cls i/ox t chz t rhz t cs free datasheet http:///
- 30 - datasheet flash memory rev. 0.9.1 k9lbg08u0e final K9GAG08U0E k9hcg08u1e 4.7 read operation ce cle r/b we ale re busy 00h col. add1 col. add2 row add1 dout n dout n+1 column address row address t wb t ar t r t rc t rhz t rr dout m t wc i/ox row add3 4.8 read operation (intercepted by ce ) ce cle r/b we ale re busy 00h dout n dout n+1 dout n+2 row address column address t wb t ar t chz t r t rr t rc 30h i/ox col. add1 col. add2 row add1 row add2 row add3 t clr t csd free datasheet http:///
- 31 - datasheet flash memory rev. 0.9.1 k9lbg08u0e final K9GAG08U0E k9hcg08u1e 4.9 random data output in a page ce cle r/b we ale re busy 00h dout n dout n+1 row address column address t w b t ar t r t rr t r c 30h/35h 05h column address dout m dout m+1 i/ox col. add1 col. add2 row add1 row add2 col. add1 col. add2 row add3 e0h t rhw t clr t whr t rea free datasheet http:///
- 32 - datasheet flash memory rev. 0.9.1 k9lbg08u0e final K9GAG08U0E k9hcg08u1e 4.10 cache read operation(1/2) ce cle r/b we ale re i/ox 1 note : 1. the column address will be reset to 0 by the 31h command input. 2. cache read operation is available only within a block. free datasheet http:///
- 33 - datasheet flash memory rev. 0.9.1 k9lbg08u0e final K9GAG08U0E k9hcg08u1e 4.11 cache read operation(2/2) ce cle r/b we ale re i/ox 1 note : 1. the column address will be reset to 0 by the 31h and 3fh command input. 2. cache read operation is available only within a block. free datasheet http:///
- 34 - datasheet flash memory rev. 0.9.1 k9lbg08u0e final K9GAG08U0E k9hcg08u1e 4.12 page program operation ce cle r/b we ale re 80h 70h i/o 0 din n din 10h m serialdata input command column address row address 1 up to m byte serial input program command read status command i/o 0 =0 successful program i/o 0 =1 error in program t prog t wb t wc t wc t wc i/ox co.l add1 col. add2 row add1 row add2 row add3 t adl t whr /f!h note : tadl is the time from the we rising edge of final address cycle to the we rising edge of first data cycle. free datasheet http:///
- 35 - datasheet flash memory rev. 0.9.1 k9lbg08u0e final K9GAG08U0E k9hcg08u1e 4.13 page program operation with random data input ce cle r/b we ale re 80h 70h i/o 0 din n din 10h m serial data input command column address row address serial input program command read status command t prog t wb t wc t wc i/ox col. add1 col. add2 row add1 row add2 col. add1 col. add2 row add3 note : 1. tadl is the time from the we rising edge of final address cycle to the we rising edge of first data cycle. t adl t adl t whr i/o 0 =0 successful program i/o 0 =1 error in program free datasheet http:///
- 36 - datasheet flash memory rev. 0.9.1 k9lbg08u0e final K9GAG08U0E k9hcg08u1e 4.14 copy-back program operation with random data input 00h i/o x 85h column address row address read status command i/o 0 =0 successful program i/o 0 =1 error in program t prog t wb t wc note : 1. tadl is the time from the we rising edge of final address cycle to the we rising edge of first data cycle. t adl t whr data 1 data n ce cle r/b we ale re i/ox free datasheet http:///
- 37 - datasheet flash memory rev. 0.9.1 k9lbg08u0e final K9GAG08U0E k9hcg08u1e 4.15 cache program operation (available only within a block) ce cle r/b we ale re 80h din n din 15h m serial data input command column address serial input program max. 127 times repeatable tcbsy twb twc r/b data address & data input 15h 80h address & data input 15h 80h address & data input 15h 80h address & data input 10h ex.) cache program t cbsy t cbsy t cbsy t prog* 2 program confirm command (true) 80h 70h 70h m row address i/ox i/ox col. add1 col. add2 row add1 row add2 col. add1 col. add2 row add1 row add2 row add3 row add3 note : 1 . tadl is the time from the we rising edge of final address cycle to the we rising edge of first data cycle. 2 . since programming the last page does not employ caching, the program time has to be that of page program. however, if the previous program cycle with t he cache data has not finished, the act ual program cycle of the last pag e is initiated only after completion of the previous cycle, which can be ex pressed as the following formula. tprog = program time for the last page + program time for the ( last -1) th page - (command input cycle time + address input cycle time + last page data loading time) / free datasheet http:///
- 38 - datasheet flash memory rev. 0.9.1 k9lbg08u0e final K9GAG08U0E k9hcg08u1e 4.16 block erase operation ce cle r/b we ale re 60h erase command read status command i/o 0 =1 error in erase d0h 70h i/o 0 busy t wb t bers i/o 0 =0 successful erase row address t wc i/ox row add1 row add2 row add3 t whr free datasheet http:///
- 39 - datasheet flash memory rev. 0.9.1 k9lbg08u0e final K9GAG08U0E k9hcg08u1e 4.17 read id operation ce cle we ale re 90h read id command maker code device code 00h ech t rea address 1cycle i/ox t ar device 4th cyc. code 3rd cyc. 5th cyc. 6th cyc. device device code (2nd cycle) 3rd cycle 4th cycle 5th cycle 6th cycle K9GAG08U0E d5h 84h 72h 50h 42h k9lbg08u0e d7h c5h 54h k9hcg08u1e free datasheet http:///
- 40 - datasheet flash memory rev. 0.9.1 k9lbg08u0e final K9GAG08U0E k9hcg08u1e 4.17.1 id definition table 3rd id data 4th id data description 1 st byte 2 nd byte 3 rd byte 4 th byte 5 th byte 6 th byte maker code device code internal chip number, cell type, numb er of simultaneously programmed pages, etc. page size, block size,redundant area size. plane number, ecc level, organization. device technology, edo, interface. description i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 internal chip number 1 2 4 8 0 0 0 1 1 0 1 1 cell type 2 level cell 4 level cell 8 level cell 16 level cell 0 0 0 1 1 0 1 1 number of simultaneously programmed pages 1 2 4 8 0 0 0 1 1 0 1 1 interleave operation between multiple chips not support support 0 1 cache operation not support support 0 1 description i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 page size (w/o redundant area ) 2kb 4kb 8kb reserved 0 0 0 1 1 0 1 1 block size (w/o redundant area ) 128kb 256kb 512kb 1mb reserved reserved reserved reserved 0 0 0 0 1 1 1 1 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 redundant area size ( byte / page size) reserved 128b 218b 400b 436b reserved reserved reserved 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 free datasheet http:///
- 41 - datasheet flash memory rev. 0.9.1 k9lbg08u0e final K9GAG08U0E k9hcg08u1e 5th id data 6th id data description i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 plane number 1 2 4 8 0 0 0 1 1 0 1 1 ecc level 1bit / 512b 2bit / 512b 4bit / 512b 8bit / 512b 16bit / 512b 24bit / 1kb reserved reserved 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 reserved 0 0 0 description i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 device version 50nm 40nm 30nm reserved reserved reserved reserved reserved 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 0 edo not support support 0 1 interface sdr ddr 0 1 reserved 0 0 0 free datasheet http:///
- 42 - datasheet flash memory rev. 0.9.1 k9lbg08u0e final K9GAG08U0E k9hcg08u1e 5.0 device operation 5.1 page read page read is initiated by writing 00h-30h to the command register along with five address cycles. the 8,628 bytes of data with in the selected page are transferred to the cache registers via data registers in less than 400 figure 6. read operation address(5cycle) 00h col. add.1,2 & row add.1,2,3 data output(serial access) data field spare field ce cle ale r/b we re t r 30h i/ox free datasheet http:///
figure 7. random data output in a page address 00h data output r/b re t r 30h/35h address 05h e0h 5cycles 2cycles data output data field spare field data field spare field i/ox col. add.1,2 & row add.1,2,3 col. add.1,2 - 43 - datasheet flash memory rev. 0.9.1 k9lbg08u0e final K9GAG08U0E k9hcg08u1e 5.2 cache read cache read is an extension of page read, which is executed with 8,628byte data regist ers, and is available only within a block. since the device has 1 page of cache memory, serial data output may be executed while data in the memory cell is read into data registers. cache read is also initiated by writing 00h-30h to the command register along w ith five address cycles. after initial power up, 00h command is latched. therefore only five address cycles and 30h command initiates that operation after initial power up. the 8,628 bytes of data wit hin the selected page are transferred to the cache registers via data registers in less than 400 free datasheet http:///
figure 8. cache read ce cle r/b we ale re i/ox note -. if the 31h command is issued to the device, the data content of the next page is transferred to the data registers during se rial data out from the cache registers, and therefore the tr (data transfer from memory cell to data register) will be reduced. 1. normal read. data is transferred from page n to cache regist ers through data registers. during this time period, the device outputs busy state for tr max. 2. after the ready/busy returns to ready, 31h command is issued and data is transferred to cache registers from data registers again. this data transfer takes tdcbsyr max and the completion of this time period c an be detected by ready/busy signal. 3. data of page n+1 is transferred to data registers from cell while the data of page n in cache registers can be read out by r e clock simultaneously. 4. the 31h command makes data of page n+1 transfer to cache regi sters from data registers after the completion of the transfer from cell to data registers. the device outputs busy state for tdcbsyr max..this busy period depends on the combination of the internal data transfer time from cell to data registe rs and the serial data out time. 5. data of page n+2 is transferred to data registers from cell while the data of page n+1 in cache registers can be read out by re clock simultaneously. 6. the 3fh command makes the data of page n+2 transfer to the cache registers from the data registers after the completion of t ransfer form cell to data registers. the device outputs busy state for tdcbsyr max.this busy period depends on the combination of the internal data transfer time from cell to data re gisters and the transfer from data registers to cache registers. 7. data of page n+2 in cache registers can be read out, but si nce the 3fh command does not transfer the data from the memory c ell to data registers, the device can accept new command input immediately after the completion of serial data out. the device has a read operation with cache registers that enab les the high speed read operation shown below. when the block add ress changes, this sequence has to be started from the beginning. 00h 30h 31h 31h 3fh 0 1 2 3 8627 0 1 2 3 8627 0 1 2 3 8627 30h 31h & re clock page n 31h & re clock page n+1 3fh & re clock page n+2 page n page n+1 page n+2 tr page row column address address column 0 page address n page address n+1 page address n+2 page n page n+1 page n+2 1 1 12 2 2 3 4 4 35 6 7 5 5 6 7 tdcbsyr tdcbsyr tdcbsyr cache register data register - 44 - datasheet flash memory rev. 0.9.1 k9lbg08u0e final K9GAG08U0E k9hcg08u1e free datasheet http:///
- 45 - datasheet flash memory rev. 0.9.1 k9lbg08u0e final K9GAG08U0E k9hcg08u1e 5.3 page program the device is programmed basical ly on a page basis, and the number of consecutiv e partial page programming operation within the same page without an intervening erase operation must not exceed 1 time for the p age. the addressing should be done in sequential order in a bloc k. a page program cycle consists of a serial data loading period in which up to 8,6 28bytes of data may be loaded into the data registers via cache regi sters, followed by a non-vol - atile programming period where the loaded data is programmed into the appropriate cell. the serial data loading period begins by inputting the s erial data input command(80h) , followed by the fi ve cycle address input s and then serial data loading. the words other than those to be programmed do not need to be loaded. the device supports random data input in a page. the column address for the next data, which will be entered, may be changed to the address which follows random data input command(85h). random da ta input may be operated multiple times regardless of how many times it is done in a page. the page program confirm command(10h) initiates the programming pr o cess. writing 10h alone without previously entering the seri al data will not initiate the programming process. the internal write state controller aut omatically executes the algorit hms and timings necessary for pr ogram and verify, thereby freeing the system controller for other tasks. once the program process starts, the read status register command may be entered to read the status reg - ister. the system controller can detect the comp letion o f a program cycle by monitoring the r/ b output, or the status bit(i/o 6) of the status register. only the read status command and reset command are valid while programmi ng is in progress. when the page program is complete, the wr ite status bit(i/ o 0) may be checked. the internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. the c ommand register remains in read status command mode until another valid command is written to the command register. figure 9. program & read status operation figure 10. random data input in a page 80h r/b address & data input i/o0 pass 10h 70h fail t prog 85h address & data input i/ox col. add.1,2 & row add1,2,3 col. add.1,2 data data "0" "1" 80h r/b address & data input i/o0 pass data 10h 70h fail t prog i/ox col. add.1,2 & row add.1,2,3 "0" "1" free datasheet http:///
- 46 - datasheet flash memory rev. 0.9.1 k9lbg08u0e final K9GAG08U0E k9hcg08u1e 5.4 copy-back program copy-back program with read for copy-back is configured to quick ly and efficiently rewrite data stored in one page without data re-loading when the bit error is not in data stored. since the ti me-consuming re-loading cycles are removed, the system performance is improved. the be nefit is especially obvi - ous when a portion of a block is updated and the rest of the block also needs to be copied to the newly assigned free block. co py-back operation is a sequential execution of read for copy-back and of copy-back program with the destination page address. a read operation with "3 5h" command and the address of the source page moves the whole 8,628byte data into the internal data buffer. a bit error is checked by sequential r eading the data output. in the case where there is no bit error, the data do not need to be reloaded. therefore copy-back pr ogram operation is initiated b y issuing page-copy data- input command (85h) with destination page address. actual progra mming operation begins after program confirm command (10h) is i ssued. once the program process starts, the read status register command (70h) may be entered to read the status register. the system controlle r can detect the com - pletion of a program cycle by monitoring the r/ b output, or the status bit(i/o 6) of the status r egister. when the copy-back program is complete, the write status bit(i/o 0) may be checked. the command register remains in read status command mode until another valid command i s written to the command register. during copy-back program, data modifica tion is possible using random data i nput command (85h) as shown below. figure 11. page copy-back program operation figure 12. page copy-back program operation with random data input r/b source address destination address there is no limitation for the number of repetition. i/ox col. add.1,2 & row add.1,2,3 col. add.1,2 & row add.1,2,3 col. add.1,2 00h add.(5cycles) 35h t r data output 85h add.(5cycles) data r/b add.(5cycles) i/o0 pass fail t prog t r source address destination address i/ox col. add.1,2 & row add.1,2,3 col. add.1,2 & row add.1,2,3 35h data output 85h add.(5cycles) 10h 70h free datasheet http:///
- 47 - datasheet flash memory rev. 0.9.1 k9lbg08u0e final K9GAG08U0E k9hcg08u1e 5.5 cache program cache program is an extension of page program, which is executed with 8,628 byte data registers, and is available onl y within a block. since the device has 1 page of cache memory, serial data input may be executed while data stored in data registers are programmed into memory ce ll. after writing the first set of data up to 8,628 byte into the selected cache registers, cache program command (15h) instead of actual page program (10h) is inputted to make cache registers free and to start internal program operation. to transfer data from cache registers to data registers, the device remains in busy state for a short period of time(tcbsy) and has its cac he registers ready for the next dat a-input while the internal pr ogramming gets started with the data loaded into data registers. read status command (70h) may be issued to find out when cache registers become ready by p olling the cache-busy status bit(i/o 6). pass/fail status of onl y the previous page is available upon the re turn to ready state. when the next set of data is inputted with the cache program command, tcbsy is affected by the progress of pendi ng internal programming. the pr ogramming of the cache register s is initiated only when the pending program cycle is finished and the data registers are available for the transfer of data from cache registers. the status bit(i/o5) for inter - nal ready/busy may be polled to identify the co mplet ion of internal programming. if the system monitors the progress of program ming only with r/ b , the last page of the target programming sequence must be programmed with actual page program command (10h). figure 13. cache program(1/2) 80h r/b 80h address & data input 15h 80h address & data input 15h 80h address & data input 10h t cbsy t cbsy t cbsy t prog* 2 70h address & data input* 15h col. add1,2 & row add1,2,3 col. add1,2 & row add1,2,3 col. add1,2 & row add1,2,3 data data data col. add1,2 & row add1,2,3 data i/ox note : 1) cache read operation is available only within a block. 2) since programming the last page does not employ caching, the program time has to be that of page program. however, if the pr e vious program cycle with the cache data has not finished, the actual program cycle of the last p age is initiated only after completion of the previous cycle, whic h can be expressed as the following formula. tprog = program time for the last page + program time for the ( last -1) th page - (program command cycle time + last page data loading time) free datasheet http:///
figure 14. cache program(2/2) - 48 - datasheet flash memory rev. 0.9.1 k9lbg08u0e final K9GAG08U0E k9hcg08u1e 15h page k cache register data register ce cle r/b we ale re 80h din n din 15h m max. 127 times repeatable free datasheet http:///
pass/fail status for each page programmed by the cache pr ogram operation can be detected by the read status operation. ? ? ? ? rev. 0.9.1 k9lbg08u0e final K9GAG08U0E k9hcg08u1e free datasheet http:///
- 50 - datasheet flash memory rev. 0.9.1 k9lbg08u0e final K9GAG08U0E k9hcg08u1e 5.6 block erase the erase operation is done on a block basis. block address loading is acco mplished in three cycles initiated by an erase setup command(60h). only block address are valid while page address is ignored. the erase confirm command(d0h) following the block address loading initi ates the internal eras - ing process. this two-step sequence of set up follo wed by execution command ensures that memory contents are not accidentally er ased due to external noise conditions. at the rising edge of we after the erase confirm command input, the internal write cont roller handles erase and erase- verify. when the erase operation is completed, the write status bit(i/o 0) ma y be checked. figure 20 details the sequence. figure 15. block erase operation 60h row add 1,2,3 r/b address input(3cycle) i/o0 pass d0h 70h t bers i/ox "0" "1" fail free datasheet http:///
- 51 - datasheet flash memory rev. 0.9.1 k9lbg08u0e final K9GAG08U0E k9hcg08u1e 5.7 read status the device contains a status register whic h may be read to find out whether program or erase operation is completed, and whethe r the program or erase operation is completed successfully. after writing 70h or f1h/f2 h command to the command register, a read cycle outputs the con tent of the status reg - ister to the i/o pins on the falling edge of ce or re , whichever occurs last. this two line control allows the system to poll the progress of each device in multiple memory connections even when r/ b pins are common-wired. re or ce does not need to be toggled for updated status. refer to table 2 for spe - cific 70h status register definitions and t able 3 for specific f1h status register definitions. the command register remains in status read mode until fur - ther commands are issued to it. therefore, if the status regi ster is read during a random read cycle, the read command(00h) sho uld be given before starting read cycles. [table 4] status register definition for 70h command note : 1) i/os defined ?not use? are recommended to be masked out when read st atus is being executed. 2) n : current page, n-1: previous page. [table 5] f1h read status register definition note : 1) i/os defined ?not use? are recommended to be masked out when read status is being executed. 2) n : current page, n-1 : previous page. [table 6] f2h read status register definition note : 1) i/os defined ?not use? are recommended to be masked out when read status is being executed. 2) n : current page, n-1 : previous page. i/o page program block erase cache program read cache read definition i/o 0 pass/fail pass/fail pass/fail(n) not use not use pass : "0" fail : "1" i/o 1 not use not use pass/fail(n-1) not use not use pass : "0" fail : "1" i/o 2 not use not use not use not use not use don?t -cared i/o 3 not use not use not use not use not use don?t -cared i/o 4 not use not use not use not use not use don?t -cared i/o 5 not use not use true ready/busy not use true ready/busy busy : "0" ready : "1" i/o 6 ready/busy ready/busy cache ready/bus y ready/busy cache ready/busy busy : "0 " ready : "1" i/o 7 write protect write protect write protect write prot ect write protect protected : "0" not protected : "1" i/o page program block erase cache program read cache read definition i/o 0 chip1 pass/fail chip1 pass/fail chip1 pass/fail(n) no t use not use pass : "0" fail : "1" i/o 1 plane pass/fail plane pass/fail plane pass/fail(n) not use not use pass : "0" fail : "1" i/o 2 not use not use not use not use not use don?t-cared i/o 3 not use not use plane pass /fail(n-1) not use not use pass : "0" fail : "1" i/o 4 not use not use not use not use not use don?t-cared i/o 5 not use not use true ready/busy not use true r eady/busy busy : "0" ready : "1" i/o 6 ready/busy ready/busy cache ready/cac he ready/busy cache ready/busy busy : "0" ready : "1" i/o 7 write protect write protect write protect write prot ect write protect protected : "0" not protected : "1" i/o page program block erase cache program read cache read definition i/o 0 chip2 pass/fail chip2 pass/fail chip2 pass/fail(n) no t use not use pass : "0" fail : "1" i/o 1 plane pass/fail plane pass/fail plane pass/fail(n) not use not use pass : "0" fail : "1" i/o 2 not use not use not use not use not use don?t-cared i/o 3 not use not use plane pass /fail(n-1) not use not use pass : "0" fail : "1" i/o 4 not use not use not use not use not use don?t-cared i/o 5 not use not use true ready/busy not use true r eady/busy busy : "0" ready : "1" i/o 6 ready/busy ready/busy cache ready/cac he ready/busy cache ready/busy busy : "0" ready : "1" i/o 7 write protect write protect write protect write prot ect write protect protected : "0" not protected : "1" free datasheet http:///
- 52 - datasheet flash memory rev. 0.9.1 k9lbg08u0e final K9GAG08U0E k9hcg08u1e 5.8 read id the device contains a product ident ification mode, initiated by writing 90h to the command register, followed by an address inp ut of 00h. six read cycles sequentially output the manufacturer code(ech), the device code, 3r d, 4th, 5th and 6th cycle id respectively. the command regi ster remains in read id mode until further commands are issued to it. figure 22 shows the operation sequence. figure 16. read id operation ce cle i/o x ale re we 90h 00h address. 1cycle maker code device code t cea t ar t rea t whr t clr device 4th cyc. code ech 3rd cyc. 5th cyc. 6th cyc. 5.9 reset the device offers a reset feature, executed by writing ffh to the command register. when the device is in busy state during ran dom read, program or erase mode, the reset operation will abort these operations. the contents of memory cells being altered are no longer valid, as the data will be partially programmed or erased. the command register is cleared to wait for the next command, and the status register is cleared to value e0h when wp is high. refer to table 7 for device status after reset operation. i f the device is already in reset state a new reset command will be accepted by the c ommand reg - ister. the r/ b pin changes to low for trst after the reset command is written. refer to figure 17 below. figure 17. reset operation ffh i/o x r/b t rst [table 7] device status device device code (2nd cycle) 3rd cycle 4th cycle 5th cycle 6th cycle K9GAG08U0E d5h 84h 72h 50h 42h k9lbg08u0e d7h c5h 54h k9hcg08u1e after reset operation mode waiting for next command free datasheet http:///
- 53 - datasheet flash memory rev. 0.9.1 k9lbg08u0e final K9GAG08U0E k9hcg08u1e 5.10 ready/ busy the device has a r/ b output that provides a hardware method of indicating the comp letion of a page program, erase and random read completion. the r / b pin is normally high but transit ions to low after program or erase command is written to the command register or random read i s started after address loading. it returns to high when the internal controller has finished the operation. the pin is an open-drain driver thereby al lowing two or more r/ b outputs to be or-tied. because pull-up resi stor value is related to tr(r/ b ) and current drain during busy(ibusy) , an appropriate value can be obtained with the fol - lowing reference chart( figure 18 ). its value can be determined by the following guidance. figure 18. rp vs tr ,tf & rp vs ibusy tr,tf [s] ibusy [a] rp(ohm) ibusy tr @ vcc = 3.3v, ta = 25 tf 100 150 200 3.6 3.6 3.6 3.6 2.4 1.2 0.8 0.6 where i l is the sum of the input currents of all devices tied to the r/b pin. rp value guidance rp(max) is determined by maximum permissible limit of tr rp(min, 3.3v part) = v cc (max.) - v ol (max.) i ol + tf tr vol 3.3v device - v ol : 0.4v, v oh : 2.4v free datasheet http:///
- 54 - datasheet flash memory rev. 0.9.1 k9lbg08u0e final K9GAG08U0E k9hcg08u1e 6.0 data protection & power up sequence the device is designed to offer pr otection from any involuntary program/erase du ring power-transitions. an internal voltage det ector disables all functions whenever vcc is below about 2v. the reset command(ffh) must be issued to all ce s as the first command after the nand flash device is powered on. each ce will be busy for a maximum of 5ms after a reset command is issu ed. in this time period, the acceptable command is 70h/f1h/f2h. wp pin provices hardware protection and is recommanded to be kept at v il during power-up and power-down. the two step command sequence for pro - gram/erase provides additional software protection. figure 19. ac waveforms for power transition v cc wp high we r/b 100 cle ce i/ox ffh note : during the initialization, the device consumes a maximum current of 50ma (icc1) free datasheet http:///
- 55 - datasheet flash memory rev. 0.9.1 k9lbg08u0e final K9GAG08U0E k9hcg08u1e 6.1 wp ac timing guide enabling wp during erase and program busy is prohibited. the eras e and program operations are enabled and disabled as follows: figure b-1. program operation figure b-2. erase operation 1. enable mode 60h d0h tww(min.100ns) 2. disable mode 60h d0h tww(min.100ns) we i/o wp r/b we i/o wp r/b 1. enable mode 80h 10h we i/o wp r/b tww(min.100ns) 2. disable mode 80h 10h tww(min.100ns) we i/o wp r/b free datasheet http:///

▲Up To Search▲

Price & Availability of K9GAG08U0E

	To Download K9GAG08U0E Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .